- Atsushi Iwata, Sanshiro Hattori, Kuniharu Uchimura, H. Shimizu and K. Ogasawara,
PCM CODEC and Filter System,
ISSCC DIGEST OF TECHNICAL PAPERS, pp. 178-179, 1980.
- Hisami Tanaka, Masao Yamasawa, Seiji Kato, Akihiko Itoh, Atsushi Iwata and Sanshiro Hattori,
PCM Coder and Decoder ICs with Switched Capacitor Filters,
ISSCC DIDEST OF TECHNICAL PAPERS, pp. 172-173, 1980.
- Atsushi Iwata, H. Kikuchi, Kuniharu Uchimura, Akihiko Morino and Masahiko Nakajima,
A Single-Chip CMOS PCM CODEC with Switched-Capacitor Filters,
ISSCC DIGEST OF TECHNICAL PAPERS, pp. 244-245, 1981.
- Naohisa Ohta, Kazunari Irie, Takehiko Uno, Atsushi Iwata and Tomonori Aoyama,
A High Quality ADM LSI CODEC at 32kbit/s for Digital Speech Communication, Proceedings ICASSP 82,
IEEE International Conference on Accoustics, Speech, and Signal Processing, 1982.
- Yukio Akazawa, Yasuyuki Matsuya and Atsushi Iwata,
A New Linearity Error Correction Technology for A/D and D/A Converter LSI,
Digest of Technical Papers 14th CSSD(Conference on Solid State Devices), pp. 69-70, 1982.
- Hironori Yamauchi, Takao Kaneko, Tsutomu Kobayashi, Atsushi Iwata and S. Ono,
An 18-bit Floating-point Signal Processor VLSI with an on-chip 512W Dual-port RAM,
Proceedings ICASSP 85, pp. 204-207, 1985.
- Hironori Yamauchi, Takao Kaneko, Junichi Takahashi and Atsushi Iwata,
Speech Signal Processor VLSI Family,
1985 IEEE International Workshop on DSP, 1985.
- Kuniharu Uchimura, Toshio Hayashi, Tadakatsu Kimura and Atsushi Iwata,
VLSI- A to D and D to A Converters with Multi-stage Noise Shaping Modulators,
Proceedings ICASSP 86, pp.1545-1548, 1986.
- Takao Kaneko, Hironori Yamauchi and Atsushi Iwata,
A 50ns Floating-point Signal Processor VLSI,
Proceedings ICASSP 86, pp. 401-404, 1986.
- Yasuyuki Matsuya, Kuniharu Uchimura and Atsushi Iwata,
A 16b Oversampling A/D Conversion Technology using Triple Integration Noise Shaping,
ISSCC DIGEST OF TECHNICAL PAPERS, pp. 48-49, 1987.
- Yukio Akazawa, Atsushi Iwata, Tsutomu Wakimoto and Hyo Ikawa,
A 400Msps 8b Flash AD Conversion LSI,
ISSCC DIGEST OF TECHNICAL PAPERS, pp. 98-99, 1987.
- Yasuyuki Matsuya, Kuniharu Uchimura and Atsushi Iwata,
A 17b Over-sampling D/A Conversion Technology using Multi-stage Noise Shaping,
1988 Symposium on VLSI Circuits, pp. 117-118, 1988.
- Tadao Nagatsuma, Tugumichi Shibata, Eiichi Sano and Atsushi Iwata,
Non-contact Electro-optic Sampling System in Subpicosecond Regime,
Conference Record of Instrumentation and Measurement Technology Conference (IMTC), pp. 152-158, 1990.
- Haruhiko Ichino, Noboru Ishihara, Yoshiki Yamauchi, Osaake Nakajima, Kouici Nagata and Atsushi Iwata,
A 10 Gb/s Decision Circuit using AlGaAs/GaAs HBT Technology,
ISSCC DIGEST OF TECHNICAL PAPERS, pp.188-189, 1990.
- Atsushi Iwata,
Neural Devices and Networks,
Germany-Japan Forum on Information Technology, 3rd Session, 1990.
- T. Watanabe, T. Morosawa, N. Shimazu, H. Morita, H. Yamauchi and A. Iwata,
Development of Reliabile and Comprehensive Direct Wafer Exposure Electron Beam System,
The 35th International Symposium on Electron, Ion, & Photon Beams, R6, 1991.
- S.Yokoyama, T.Nagata, T.Namba, Y.Kuroda, T.Doi, K.Miyake, S.Miyazaki, A.Iwata, T.Ae, M.Konyanagi and M.Hirose,
Optical Interconection on Silicon LSI Chips,
Proceesing of Photonics West'95,1995.
- S. Yokoyama, K. Miyake, T. Nagata, H. Sakaue, S. Miyazaki, Y. Horiike, A. Iwata, T. Ae. M. Konyanagi and M. Hirose,
GaAs/Si Optoelectronic Design and Development at Hiroshima University,
Int. Workshop: Semoconductor Characterization, NIST, 1995.
- T. Doi, T. Namba, A. Uchara, M.Nagata, S.Miyazaki, K.Shibahara, S.Yokoyama, A.Iwata, T.Ae and M.Hirose,
Optically Interconnected Kohonen Net for Pattern Recognition,
Extended Abstracts of the 1995 International Conference on Solid State Devices and Materials
(SSDM'95), p.1075, 1995.
- T. Namba, A. Uehara, T. Doi, T.Nagata, Y.Kuoda, S.Miyazaki, K.Shibahara, S.Yokoyama, A.Iwata and M.Hirose,
High-Efficiecy Micromirrors and Branched Optical Waveguides on Si Chips,
Extended Abstracts of 1995 International Conference on Solid State Devices and Materials (SSDM'95), p.830. 1995.
- A. Iwata, T. Doi, M. Nagata et. al.,
Photo-Electric Crossbar Switches for Multi-Processor Systems,
International Conference on Applications of Photonics Technology 1996 (ICAPT' 96), pp.105-107, 1996.
- M. Nagata, A. Iwata,
A minimum Distance Search Circuit using Dual-Line PWM Signal Processing and Charge Packet Counting Technique,
International Solid-State Circuits Conference (ISSCC'97) , pp.42-43, 1997.
- A. Iwata,
Integrated Optical Interconnections,
International Workshop on Future Information Processing Technologies, Aug. 1997.
- T. Doi, A. Uehara, Y. Takahashi, S. Yokoyama, A. Iwata and M. Hirose,
Experimental Pattern Recognition System using Bi-directional Optical Bus Lines,
Extended Abstracts of the 1997 Int'l Conf. on Solid State Devices and Materials (SSDM'97), pp.388-389, 1997.
- T. Morie, H. Ando, S. Sakabayashi, M. Nagata and A. Iwata,
A New PWM Technique Implementing Arbitrary Nonlinear Dynamics and its Application to Oscillator Neuron,
The 2nd R.I.E.C. International Symposium on Design and Architecture of Information Processing,
Systems based on the Brain Information Principles, Sendai, March 16-18, 1998.
- A. Iwata, N. Sakimura, M. Nagata and T. Morie,
An Architecture of Delta Sigma A-to-D Converters using a Voltage Controlled Oscillator
as a Multi-bit Quantizer,
ISCAS 98, TPA14-5, pp. I-389-392, June 2, 1998.
- T. Yamanaka, T. Morie, M. Nagata and A. Iwata,
A Stochastic Associative Memory Using Single-Electron Devices and Its Application to Pattern Association,
Extended Abstracts of the Int. Conf. Solid State Devices and Materials(SSDM'98),
pp. 190-191, Hiroshima, Sept. 8, 1998.
- T. Morie, S. Sakabayashi, H. Ando, M. Nagata and A. Iwata,
Pulse Modulation Circuit Techniques for Nonlinear Dynamical Systems,
Proc. International Symposium on Nonlinear Theory and its Application (NOLTA'98),
pp. 447-450, Crans-Montana, Sept. 16, 1998.
- T. Morie, J. Funakoshi, M. Nagata and A. Iwata,
LSI Implementation of Neural Networks Using A Pulse-Width Modulation Method,
Proc. 5th International Conference on Soft Computing and Information/Intelligent Systems (IIZUKA'98),
pp. 118-121, Iizuka, Oct. 18, 1998.
- S. Sakabayashi, T. Morie, M. Nagata and A. Iwata,
Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation,
Proc. 5th International Conference on Neural Information Processing (ICONIP'98),
pp. 582-585, Kitakyushu, Oct. 21, 1998.
- H. Ando, T. Morie, M. Nagata and A. Iwata,
Oscillator Networks for Image Segmentation and their Circuits using Pulse Modulation Methods,
Proc. 5th International Conference on Neural Information Processing (ICONIP'98),
pp. 586-589, Kitakyushu, Oct. 21, 1998.
- A. Iwata, M. Nagata, M. Homma, H. Nakamoto, H. Higashi, N. Takeda and T. Morie
A CMOS Intelligent Feature Associative Processor with Functional Image Sensing and
A-D merged Parallel Architecture,
International Symposium on Future of Intellectual Integrated Electronics, pp.401-411, Sendai, March 14-17, 1999.
- T. Morie, S. Sakabayashi, M. Nagata and A. Iwata,
Nonlinear Dynamical Systems Utilizing Pulse Modulation Signals and a CMOS Chip Generating Arbitrary Chaos,
Proc. 7th Int. Conf. on Microelectronics for Neural, Fuzzy and Bio-inspired Systems (MicroNeuro'99),
pp. 254-260, Granada, Spain, Apr. 9, 1999.
- M. Nagata, Y. Kashima, D. Tamura, T. Morie and A. Iwata,
Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC Environment,
IEEE 1999 Custom Integrated Circuits Conference, #26.5, pp. 575-578, San Diego, USA, May 17-19, 1999.
- M. Nagata, M. Homma, N. Takeda, T. Morie and A. Iwata,
A Smart CMOS Imager with Pixel Level PWM Signal Processing,
1999 Symposium on VLSI Circuits Dig. of Technical Papers, #14.4, pp. 141-144, Kyoto, June 17-19, 1999.
- H. Ando, M. Miyake, T. Morie, M. Nagata and A. Iwata,
A Nonlinear Oscillator Network Circuit for Image Segmentation with Double-threshold Phase Detection,
Proc. 9th Int. Conf. on Artificial Neural Networks (ICANN'99), pp. 655-660, Edinburgh, Sept. 7-10, 1999.
- H. Nakamoto, M. Nagata, T. Morie and A. Iwata,
A Pattern Matching Processor Using Analog-Digital Merged Architecture Based on Pulse Width Modulation
Extended Abstracts of the 1999 Int. Conf. Solid State Devices and Materials (SSDM'99),
pp. 98-99, Tokyo, Sept. 21, 1999.
- T. Yamanaka, T. Morie, M. Nagata and A. Iwata,
A Stochastic Association Circuit Using PWM Chaotic Signals,
Extended Abstracts of the 1999 Int. Conf. Solid State Devices and Materials (SSDM'99),
pp. 100-101, Tokyo, Sept. 21, 1999.
- A. Iwata, M. Nagata, H. Nakamoto, N. Takeda, M. Homma, H. Higashi and T. Morie,
A Feature Associative Processor for Image Recognition based on A-D merged Architecture,
VLSI: system on a chip:
IFIP Int. Conf. on VLSI 1999, pp.77-88, Lisbon, Dec. 3, 1999.
- T. Morie, T. Matsuura, S. Miyata, T. Yamanaka, M. Nagata and A. Iwata,
Quantum Dot Structures Measuring Hamming Distance for Associative Memories,
Surfaces and Interfaces of Mesoscopic Devices (SIMD'99), Hawaii, Dec. 10, 1999.
- N. Takeda, M. Homma, M. Nagata, T. Morie, and A. Iwata,
A Smart Imager for the Vision Processing Front-end, Proc.
Asia and South Pacific Design Automation Conference (ASP-DAC2000), A1.10,
pp. 19-20, Jan. 2000, Yokohama.
- K. Murakoshi, T. Morie, M. Nagata and A. Iwata,
An Arbitrary Chaos Generator Core Circuit Using PWM/PPM Signals,
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2000), A1.12,
pp. 23-24, Jan. 2000, Yokohama.
- M. Nagata and A. Iwata,
Substrate Crosstalk Analysis in Mixed Signal CMOS Integrated Circuits (Embedded Tutorial),
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2000), E7.3,
pp. 623-629, Jan. 2000, Yokohama.
- M. Nagata, K. Hijikata, J. Nagai, T. Morie, and A. Iwata,
Reduced Substrate Noise Digital Design for Improving Embedded Analog Performance,
IEEE 2000 International Solid-State Circuits Conference Digest of Technical Papers, TP13.6,
pp. 224-225, Feb. 2000, San Francisco.
- M. Nagata, J. Nagai, T. Morie, and A. Iwata,
Quantitative Characterization of Substrate Noise for Physical Design Guides in Digital Circuits,
Proc. IEEE 2000 Custom Integrated Circuits Conference, #5-7, pp. 95-98, May. 2000.
- A. Iwata, M. Nagata, N. Takeda, M. Homma, and T. Morie,
Pulse Modulation Circuit Architecture and its Application to Functional Image Sensors,
Proc. IEEE International Symposium on Circuits and Systems 2000, #0113-4, pp. II-301-304, May. 2000, Geneva.
- T. Matsuura, T. Morie, M. Nagata, and A. Iwata,
A Multi-Quantum-Dot Associative Circuit Using Thermal-Noise Assisted Tunneling,
Extended Abstracts of the 2000 Int. Conf. Solid State Devices and Materials (SSDM2000),
pp. 306-307, Sendai, Aug. 30, 2000.
- K. Katayama, M. Nagata, T. Morie, and A. Iwata,
A High-Resolution Hadamard Transform Circuit Using Pulse Width Modulation Technique,
Extended Abstracts of the 2000 Int. Conf. Solid State Devices and Materials (SSDM2000),
pp. 366-367, Sendai, Aug. 30, 2000.
- H. Ando, T. Morie, M. Miyake, M. Nagata, and A. Iwata,
Image Object Extraction using Resistive-Fuse and Oscillator Networks and a Pulse-Modulation Circuit
for their LSI Implementation,
Extended Abstracts of the 2000 Int. Conf. Solid State Devices and Materials (SSDM2000),
pp. 368-369, Sendai, Aug. 30, 2000.
- T. Morie, M. Miyake, S. Nishijima, M. Nagata and A. Iwata,
A Multi-Functional Cellular Neural Network Circuit Using Pulse Modulation Signals for Image Recognition,
Proc. 7th International Conference on Neural Information Processing (ICONIP-2000),
pp. 613-617, Taejon, Nov. 16, 2000.
- T. Morie, T. Matsuura, M. Nagata and A. Iwata,
Quantum Dot Structures Measuring Hamming Distance for Associative Memories (Invited),
Extended Abstracts, 4th International Workshop on Quantum Functional Devices (QFD2000),
pp. 210-213, Kanazawa, Nov. 17, 2000.
- M. Nagata, T. Ohmoto, J. Nagai, T. Morie, and A. Iwata,
Test Circuits for Substrate Noise Evaluation in CMOS Digital ICs,
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), A1.7, pp.13-14, Jan. 2001, Yokohama.
- Y. Murasaka, M. Nagata, T. Ohmoto, T. Morie, and A. Iwata,
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation,
Proc. Intern. Symp. Quality Electronic Design (ISQED2001), 4C.3, pp. 482-487, Mar. 2001, San Jose.
- M. Nagata, T. Ohmoto, Y. Murasaka, T. Morie, and A. Iwata,
Effects of Power-Supply Parasitic Components on Substrate Noise Generation in Large-Scale Digital Circuits,
Symp. on VLSI Circuits, #15-1, pp. 159-162, June 2001, Kyoto.
- A. Iwata, T. Morie, and M. Nagata,
Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies (Invited)
Extended Abstracts of the 2001 Int. Conf. Solid State Devices and Materials (SSDM2001),
pp. 88-89, Tokyo, Sept. 26, 2001.
- T. Morie, M. Miyake, M. Nagata, and A. Iwata,
A 1-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation,
Extended Abstracts of the 2001 Int. Conf. Solid State Devices and Materials (SSDM2001),
pp. 90-91, Tokyo, Sept. 26, 2001.
- T. Morie, M. Nagata, and A. Iwata,
Design of a Pixel-Parallel Feature Extraction VLSI System for Biologically-Inspired Object Recognition Methods,
Proc. International Symposium on Nonlinear Theory and its Application (NOLTA2001),
pp. 371-374, Zao, Oct. 31, 2001.
- T. Morie, T. Matsuura, M. Nagata, and A. Iwata,
An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures,
Neural Information Processing Systems (NIPS2001) Abstracts of Papers, p. 56, Vancouver, Canada, Dec. 4, 2001.
- A. Iwata,T.Oomoto,Y. Murasaka and M. Nagata,
Measurement and SimulationTechniques for Cross-talk Noise on Mixed Signal SoC,
SEMI Technorogy Symposium(STS2001) Proceedings, session5 p35-37,Chiba,Dec 5-7, 2001.
- M. Nagata, Y. Murasaka, Y. Nishimori, T. Morie, and A. Iwata,
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models,
Proc. 7th Asia and South Pacific Design Automation Conf, pp. 71-76, Bangalore, Jan. 2002.
- T. Morie, J. Umezawa, T. Nakano, H. Ando, M. Nagata, and A. Iwata,
A Biologically-Inspired Object Recognition System Using Pixel-Parallel Feature Extraction VLSIs,
International Invitational Workshop on Intelligent Interface Devices, pp. 35-37, Kitakyushu, March 14, 2002.
- M. Nagata, T. Morie, and A. Iwata,
Modeling Substrate Noise Generation in CMOS Digital Integrated Circuits,
IEEE 2002 Custom Integrated Circuit Conf, Orlando, May 2002.
- T. Morie, T. Matsuura, M. Nagata, and A. Iwata,
A Multi-Nanodot Floating-Gate MOSFET Circuit for Spiking Neuron Models,
2002 IEEE Silicon Nanoelectronics Workshop, pp.53-54, Honolulu, June 9, 2002.
- T. Morie, T. Matsuura, M. Nagata, and A. Iwata,
An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures,
Advances in Neural Information Processing Systems 14, MIT Press, Cambridge, MA, 2002.
- K. Katayama and A. Iwata,
A High-Resolution Hadamard Transform Chip,
International Conference on Solid State Devices and Materials (SSDM), pp. 372-373, Nagoya, Sept.17-19, 2002.
- T. Maeda, A. Iwata, M. Kawabata, and S. Orisaka,
A 10-GHz Bipolar VCO with Reduced Phase Noise,
International Conference on Solid State Devices and Materials (SSDM), pp. 370-371, Nagoya, Sept.17-19, 2002.
- H. Ando, T. Morie, M. Nagata, and A. Iwata,
An Image Region Extraction LSI Based on a Merged/Mixed-Signal Nonlinear Oscillator Network Circuit,
28th European Solid-State Circuits Conference (ESSCIRC 2002), CP.11, pp. 703-706, Florence, Italy, Sept. 26, 2002.
- K. Katayama and A. Iwata,
Pulse Coupled Neural Network using Coupled Phase Locked Loop,
International Symposium on Nonlinear Theory and its Applications (NOLTA), pp. 853-856, Xi'an, Oct. 7-11, 2002.
- T. Morie, T. Matsuura, M. Nagata, and A. Iwata,
An Efficient Clustering Algorithm using Stochastic Association and Its Implementation
using 3D-Nanodot-Array Structures,
2003 RCIQE International Seminar on Quantum Nanoelectronics for Meme-Media-Based Information Technologies,
pp. 59-63 , Sapporo, Feb. 13, 2003.
- A. Iwata, H.J.Mattaushe, M.M.Mattaushe and H. Sunami,
Target and Research Plan of 21st Century Center of Excellence on Nanoelectronics
for Tera-bit Infomation Processing
The 1st Hiroshima International Workshop on Nanoelectronics for Terabit Information Processing,
pp.2-14, Hiroshima, March 17, 2003.
- A. Iwata and M. Sasaki,
3-Dimensional global/local wireless interconnection for hierarchical processing systems,
Proc. of the 1st Hiroshima International Workshop on Nanoelectronics for tera bit Information Processing,
pp.111-116, Hiroshima, March 17, 2003.
- H. Ando, T. morie and A. Iwata,
Image Segmentation/Extraction using Nonlinear Pixcel-Parallel Networks and theit VLSI Implementation,
Proc. of the 1st Hiroshima International Workshop on Nanoelectronics for tera bit Information Processing,
pp.117-120, Hiroshima, March 17, 2003.
- A. Iwata,
(Invited) Advanced Design for Analog-RF and Digital Mixed LSIs- Crosstalknoise Evaluaiton and Reduction,
Proc. of the Workshop on SASIMI, pp.17-22, Hiroshima, April 3, 2003.
- T. Yoshida, and A. Iwata,
A Design of Neural Signal Sensing LSI with Multi-Input-Channels,
Proc. of the Workshop on SASIMI, pp. 206-210, Hiroshima, April 3, 2003.
- T. Yoshida, T. Mashimo, M. Akagi, A. Iwata, M. Yoshida and K. Uematsu,
A Design of Neural Signal Sensing LSI with Multi-Input-Channels,
Proc. of the Workshop on SASIMI, pp. 206-210, Hiroshima, April 3, 2003.
- S. Kameda, M. Sasaki and A. Iwata,
A Multi-chip Vision System with a PWM-based Line Parallel Interconnection,
Proc. Second Hiroshima International Workshop on Nanoelectronicsfor Tera-Bit Information Processing,
pp.18-19, 2004.
- T. Morie, T. Nakano, J. Umezawa, and A. Iwata,
Gabor-Type Filtering Using Transient States of Cellular Neural Networks,
Intelligent Automation and Soft Computing, Vol. 10, No. 2, pp. 95-104, 2004.
- K. Korekado, T. Morie, O. Nomura, H. Ando, T. Nakano, M. Matsugu, and A. Iwata,
A VLSI Convolutional Neural Network for Image Recognition Using Merged/Mixed Analog-Digital Architecture,
Int. J. Fuzzy and Intelligent Systems, Vol. 15, No. 3/4, pp. 173-179, 2004.
- T. Morie, J. Umezawa, and A. Iwata,
Gabor-Type Filtering Using Transient States of Cellular Neural Networks,
Intelligent Automation and Soft Computing, Vol. 10, No. 2, pp. 95-104, 2004.
- M. Shiozaki, T. Mukai, M. Ono, M. Sasaki and A. Iwata,
A 2Gbps and 7-multiplexing CDMA Serial Receiver Chip for Highly Flexible Robot Control System,
2004 Symposium on VLSI Circuits,Digest of Technical Papers,
pp. 194-197,Honolulu, Hawaii, June 17-19, 2004.
- T. Morie, J. Umezawa, and A. Iwata,
A Pixel-Parallel Image Processor for Gabor Filtering Based on Merged Analog-Digital Architecture,
2004 Symposium on VLSI Circuits, Digest of Technical papers,
pp. 212-213, #14-1, Honolulu, Hawaii, June 18, 2004.
- T. Morie, T. Nakano, J. Umezawa, and A. Iwata,
Gabor Filtering Using Cellular Neural Networks and its Application to Face/Object Recognition,
World Automation Congress, #IFMIP075, Seville, Spain, June 28-July 1, 2004.
- K. Sasaki, T. Morie, and A. Iwata,
A Spiking Neural Network with Negative Thresholding and Its Application to Associative Memory,
2004 IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS2004),
pp. III-89 - III-92, Hiroshima, July 25-28, 2004.
- O. Nomura, T. Morie, K. Korekado, M. Matsugu, and A. Iwata,
A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition,
Int. Conf. on Knowledge-Based Intelligent Information and Engineering Systems, (KES'2004),
Wellington, New Zealand, Sep 22-24, 2004.
- T. Yoshida, T. Mashimo, M. Akagi, A. Iwata, M. Yoshida and K. Uematsu,
A Low Noise Amplifier using Chopper Stabilization for a Neural Sensor LSI,
2004 International Conference on Solid State Devices and Materials pp.148-149, Sep, 2004, Tokyo.
- A. Iwata, M. Sasaki, T. Kikkawa, S. Kameda, H. Ando, K. Kimoto, D. Arizono and H. Sunami,
A 3D-Integration Scheme Utilizing Wireless Interconnections for Implementing Hyper Brains,
IEEE 2005 International Solid-State Circuits Conference Digest of Technical Papers, TP14.4,
pp. 262-263, Feb 6-10, 2005, San Francisco.
- M. Nagata, M. Fukazawa, N. Hamanishi, M. Shiochi, T. Iida, J. Watanabe, Y. Murasaka and A. Iwata,
Substrate Integrity Beyond 1GHz,
IEEE 2005 International Solid-State Circuits Conference, Digest of Technical Papers,
TP14.6, pp. 266-267, Feb 6-10, 2005, San Francisco.
- T. Yoshida, M. Akagi, M. Sasaki and A. Iwata,
A 1V Supply Successive Approximation ADC with Rail-to-Rail Input Voltage Range,
Proceedings of 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005),
pp. 192-195, May 24, 2005, Kobe.
- T. Yoshida, Y. Masui, T. Mashimo, M. Sasaki and A. Iwata,
A 1V Supply 50nV/√Hz Noise PSD CMOS Amplifier Using Noise Reduction Technique
of Autozeroing and Chopper Stabilization,
IEEE 2005 Symposium on VLSI Circuits, June 16, 2005, Kyoto.
- K. Korekado, T. Morie, O. Noura, T. Nakano, M. Matsugu and A. Iwata,
An Image Filtering Processor for Face/Object Recognition Using Merged/Mixed Analog-Digital Architecture,
IEEE 2005 Symposium on VLSI Circuits June 17, 2005, Kyoto.
- D. Kosaka, M. Nagata, Y. Hiraoka, I. Imanishi, M. Maeda, Y. Murasaka and A. Iwata,
Isolation Strategy against Substrate Coupling in CMOS Mixed-Signal/RF Circuits,
IEEE 2005 Symposium n VLSI Circuits, June 17, 2005, Kyoto.
- M. Sasaki and A. Iwata,
A 0.95mW/1.0Gbps Spiral-Inductor Based Wireless Chip-Interconnect with Asynchronous Communication Scheme,
IEEE 2005 Symposium on VLSI Circuits, June 17, 2005, Kyoto.
- M. Hori, M. Ueda and A. Iwata,
A stochastic computing chip for measurement of Manhattan distance,
Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials,
pp. 316-317, Kobe, 2005.
- K. Sasaki, S. Kameda and A. Iwata,
Stereo Matching Algorithm Using a Weighted Average of Costs Aggregated by Various Window Sizes,
7th Asian Conference on Computer Vision, Proceedings PartII, pp. 771-780, Jan. 13-16, 2006, Hyderabad, India.
- M. Sasaki, M. Shiozaki, A. Mori, A. Iwata, and H. Ikeda,
17Gfz Fine Grid Clock Distribution with Uniform-Amplitude Standing-Wave Oscillator,
IEEE 2006 Symposium on VLSI Circuits Digest of Technical Papers, pp. 124-125, June 15-17, 2006, Honolulu.
- Y. Masui, T. Yoshida, M. Sasaki and A. Iwata,
A 0.6V Supply CMOS Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization,
Solid State Devices and Materials, September 14, 2006, YOKOHAMA.
- T. Yoshida, N. Ishida, M. Sasaki and A. Iwata,
Low-Voltage, Low-Phase-Noise Ring-VCO using 1/f-noise Reduction Techniques,
2006 International Conference on Solid State Devices and Materials, pp. 376-377,
Sept. 14, 2006, YOKOHAMA.
- M.Sasaki, M.Shiozaki, A.Mori, A.Iwata, and H.Ikeda,
12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique,
ISSCC Digest of Technical Papers, pp.180-181, Feb 6, 2007, San Francisco.
- T. Sato, A. Inoue, T. Shiota, T. Inoue, Y. Kawabe, T. Hashimoto, T.Imamura,Y. Murasaka, M. Nagata,and A. Iwata,
On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Application,
ISSCC Digest of Technical Papers, pp. 290-291, Feb 6, 2007, San Francisco.
- H. Ando, S. Kameda, D. Arizono, N. Fuchigami, K. Kaya, M. Sasaki, and A. Iwata,
PCA-based Object Detection/Recognition Chip for Wireless Interconnected 3-D Integration,
Solid State Devices and Materials, September 21 2007, Tsukuba, Ibaraki, Japan.
- A. Toya, Y. Murasaka, T. Ohmoto and A. Iwata,
Evaluation of Digital Crosstalk Noise on a Differential Input VCO,
Solid State Devices and Materials, September 20, 2007, Tsukuba.
- Y.Masui, T.Yoshida, and A. Iwata,
A 2.0 Vpp Input,0.5V Supply Delta Amplifier with A-to-D Conversion,
IEEE Asian Solid-State Circuits Conference, November 5, 2008, Fukuoka.
- K. Gotoh, H. Ando and A. Iwata,
A 10-b 30-MS/s 3.4-mW Pipelined ADC with 2.0-Vpp Full-swing Input at 1.0-V Supply,
IEEE Asian Solid-State Circuits Conference, November 4, 2008, Fukuoka.
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T. Yoshida, Y. Masui, R. Eki, A. Iwata, M. Yoshida and K. Uematsu,
A Neural Signal Detection Amplifier with Low-Frequency Noise Suppression,
Proceedings of 2009 IEEE International Symposium on Circuits and Systems (ISCAS2009), pp.661-664, 2009.
- M. Shiozaki, and A. Iwata,
Vertical Inductor Design with Trough Silicon VIas and its Appplication to
3D inductive-coupled Standing-Wave-Oscllator,
International Conference on Electronic Pacakging(ICEP2010), May 12-14, 2010, Sapporo.
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K. Sueishi, T. Yoshida, A. Iwata, K. Matsushita, M. Hirata, and T. Suzuki,
A 60dB SFDR Low-Noise Amplifier with Variable Bandwidth for Neural Recording Systems,
Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials, pp.812-813,
Tokyo, 2010.
- S. G. Ryu, T. G. Tsuru, S. Nakajima, A. Takeda, Y. Arai, T. Miyoshi, R. Ichimiya, Y. Ikemoto, R. Takashima,
T. Imamura, T. Ohmoto and A. Iwata,
Develpment of X-ray Imaging Spectroscopy Sensor with SOI CMOS Technology,
IEEE NSS 2010, Oct. 2, 2010, Knoxville.
- S. Nakajima, S. G. Ryu, T. G. Tsuru, Y. Arai, A. Takeda, H. Nakajima, H. Tunemi, J. Doty,
T. Imamura, T. Ohmoto T. Maeda and A. Iwata,
Development of a built-in Analog-to-Digital Converter for a X-ray Astronomy Detector
with the SOI CMOS Technology,
IEEE Neuclear Science Symp. Conference Record, pp. 1201-1203, 2011.
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S. G. Ryu; A. Takeda; S. Nakashima; T. Go Tsuru; Y. Ikemoto; Y. Arai; T. Imamura; T. Ohmoto; A. Iwata,
Design and development of trigger-driven readout with X-ray SOI pixel sensor,
Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE, Pages: 1197-1200
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M. Omodani, T. Kudo, K. Moria, Y. NagaiI, T. Hatsui, K. Kobayashi, T. Imamura, T. Ohmoto, A. Iwata,
S. Ono, Y. Kirihara, M. Okihara, M. Nagasaki,
Development of Silicon-On-Insulator PHoton Imaging Array Sensor (SOPHIAS) for X-ray Free-Electron Laser,
International Workshop on Semiconductor Pixel Detectors for Particles and Imaging (PIXEL2012)
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A. Takeda,Y. Arai, T. Go Tsuru, T. Tanaka, S. Nakashima, H. Matsumura, T. Imamura,
T. Ohmoto, A. Iwata,
Development of new circuit with CSA for X-ray astronomical SOI pixel detector-improving energy resolution,
2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC)
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T. Hatsui, M. Omodani, T. Kudo, K. Kobayashi, T. Imamura,T. Ohmoto,A. Iwata,S. Ono, Y. Kirihara,
T. Kameshima, H. Kasai, N. Miura, N. Kuriyama, M. Okihara, Y. Nagatomo, M. Nagasaki, T. Watanabe, M. Yabashi,
A direct-detection X-ray CMOS image sensor with 500 μm thick high resistivity silicon,
2013 INTERNATIONAL IMAGE SENSOR WORKSHOP_03-5_058