岩田���公表物

論文

1. 岩田　����吉村　寛，柳川文彦
   多周波受信器用混成集積化����アク����ブＢ����の設��
   信学��(C), Vol. 60-C, No. 6, pp. 359-366, (1977) [pdf]
2. 岩田　����中山　����斉藤保直��丹生和男
   レーザによる混成Ｉ��化Ｒ��アク����ブフィルタの機��トリミング
   信学��(C), Vol. 60-C, No. 11, pp. 669-675, (1977) [pdf]
3. Goichi Tatsuno, Minpei Fujinami, Atsushi Iwata and Kaoru Kinamari
   Precision Electron Beam Exposure System, EB-52
   Revue de Physique Appliquee, Vol. 13, pp. 705-708, (1978)
4. Atsushi Iwata, Kuniharu Uchimura, Sanshiro Hattori, Hiroaki Shimizu and Kazuo Ogasawara
   Low Power PCM CODEC and Filter System,
   IEEE J. of Solid-State Circuits, Vol. SC-16, No. 2, pp. 73-79, (1981) [pdf]
5. Atsushi Iwata, Hiroyuki Kikuchi, Kuniharu Uchimura, Akihiko Morino and Masahiko Nakajima,
   A Single-chip CODEC with Switched-Capacitor Filters,
   IEEE J. of Solid-State Circuits, Vol. SC-16, No. 4, pp. 315-321, (1981) [pdf]
6. Yukio Akazawa, Yasuyuki Matsuya and Atsushi Iwata,
   New Linearity Error Correction Technology for A/D and D/A Converter LSI,
   JJAP,Vol. 22, Sup.22-1, pp. 115-119, (1983)
7. Kazunari Irie, Takehiko Uno, Kuniharu Uchimura and Atsushi Iwata,
   A Single-chip ADM LSI CODEC,
   IEEE J. of Solid-State Circuits, Vol. SC-18, No. 1, pp. 33-39, (1983)
8. Yukio Akazawa, Hiroyuki Kikuchi, Atsushi Iwata, Takashi Matuura and Toru Takahashi,
   Low Power 1 GHz Frequency Synthesizer LSIs,
   IEEE J. of Solid-State Circuits, Vol. SC-18, No. 1, pp. 115-121,　(1983) [pdf]
9. 金子孝夫��菊��博行，岩田　��,
   多重化スイ����トキャパシタフィルタの設計��,
   信学��(��), Vol. J67-C, No. 7, pp. 588-595, (1984) [pdf]
10. 松谷康之，赤沢幸����岩田　��, 高精度,高速Ｃ��������チ�����/��,��/��変換器-全����タル精度補正�� (LECS),
    信学�� (��), Vol. J69-C, No. 5, pp. 531-539, (1986) [pdf]
11. Junichi Takahashi, Takashi Kimura, Sanshiro Hattori and Atsushi Iwata,
    A Ring Array Processor Architecture for Highly Parallel Dynamic Time Warping,
    IEEE Trans. ASSP, Vol. 34, No. 5, pp. 1310-1318, (1986)
12. Yasuyuki Matsuya, Kuniharu Uchimura and Atsushi Iwata,
    A 16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping,
    IEEE J. of Solid-State Circuits, Vol. SC-22, No. 6, pp. 921-929, (1987) [pdf]
13. Kuniharu Uchimura, Toshio Hayashi, Tadakatsu Kimura and Atsushi Iwata,
    Oversampling A-to-D and D-to-A Converters with Multi-stage Noise Shaping Modulators,
    IEEE Trans. ASSP, Vol. 36, No. 12, pp. 1899-1905, (1988) [pdf]
14. Eiichi Sano, Tuneo Tsukahara and Atsushi Iwata,
    Performance Limits of Mixed Analog/digital Circuits with Scaled MOSFETs,
    IEEE J. of Solid-State Circuits, Vol. SC-23, No. 4, pp. 942-949, (1988) [pdf]
15. Kenji Nakayama, Atsushi Iwata and Takeshi Yanagisawa,
    (Invited) Present and Future Trends in Integrated Analog Signal Processing Circuits,
    IEICE Trans. Vol. E71, No. 12, pp. 1177-1188, (1988)
16. 金子孝夫��山����紀��岩田　��.
    正規化浮動少数点��������シグナルプロセ������DSSP1
    信学�� (B),Vol. J72-B-I, No. 1, pp. 67-73, (1989)
17. Yasuyuki Matsuya, Kuniharu Uchimura,　Atsushi Iwata andTakao Kaneko,
    A 17-bit Oversampling D-to-A Conversion Technology using Multistage Noise Shaping,
    IEEE J. of Solid-State Circuits, Vol. SC-24, No. 4, pp. 969-975, (1989)[pdf]
18. 岩田　����松谷康��,
    オー����オ用1ビッ��AD, DA変換技��(1)
    JAS Journal, Vol, 29, No.1, pp15-21, 1989.
19. 岩田　����松谷康��,
    オー����オ用1ビッ��AD, DA変換技��(2)
    JAS Journal, Vol, 29, No.2, pp.33-39, 1989.
20. Tadao Nagatsuma, Tsugumichi Shibata, Eiichi Sano and Atsushi Iwata,
    Subpicosecond Sampling using a Noncontact Electro-optic Probe,
    J. Appl. Phys. Vol. 66, No. 9, 　pp. 4001-4009, (1989)
21. Eiichi Sano, Tadao Nagatsuma, Tsugumichi Shibata and Atsushi Iwata,
    Generation of Picosecond Electrical Pulses by Pulse-forming Optoelectronic Device,
    Appl. Phys. Lett., Vol. 55, No. 2, pp.151-152, (1989)
22. M. Koga, T. Matsumoto, Y. Amemiya, A. Iwata and H. Miyao,
    High-Speed Analogue Neural-Network LSI Employing Super-Selfaligned Si Bipolar Process Technology,
    Electronics. Lett.,Vol. 27, No. 18, pp. 1678-1679, (1991)
23. O. Fujita, Y. Amemiya and A. Iwata,
    Characteristics of Floating Gate Device as Analogue Memory for Neural Networks,
    Electron. Lett., Vol. 27, No. 11, pp. 924-925, (1991)
24. T. Watanabe, T. Morosawa, N.. Shimazu, H. Morita, H. Yamauchi and A. Iwata,
    Reliability Enhancements for the Direct Wafer Exposure Electron Beam System EB60,
    J. of Vac. Sci. Technology B Vol.9, No.6, pp. 3028-3032, (1991)
25. H. Yamauchi, T. Morosawa, T. Watanabe and A.i Iwata,
    Real-Time Feed- Forward Control LSIs for a Direct Wafer Exposure Electron Beam System,
    IEICE Trans. Electron. Vol. E76-C, No. 1, pp. 124-135, (1993)
26. A. Iwata and I. Hayashi,
    Optical Interconnections as a New LSI Technology,
    IEICE Trans. Electron. Vol. E76-C, No. 1, pp. 90-99, (1993) [pdf]
27. A. Iwata,
    Optical Interconnection for ULSI Techmology Innovation,
    Optoelectronics -device and Technologies, Vol. 9, No.1, pp.39-54, (1994)
28. A. Iwata and M. Nagata,
    A Concept of Analog-Digital merged Circuit Architecture for Future VLSI's,
    IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences,
    Vol. E79-A, No.2, pp.145-157, (1996). [pdf]
29. T. Doi, T. Namba, A. Uehara, M. Nagata, S. Miyazaki, K. Sibahara, S. Yokoyama, A. Iwata, T. Ae and M. Hirose,
    Optically Interconnected Kohonen Net for Pattern Recognition,
    JJAP, Vol.35. Part I, No. 2B, pp. 1405-1409 (1996)
30. T. Namba, A. Uehara, T. Doi, T. Nagata, Y. Kuroda, S. Miyazaki, K. Sibahara, S. Yokoyama, A .Iwata and M. Hirose,
    High-Efficiency Micromirrors and Branched Optical Waveguides on Si Chips,
    JJAP, Vol.35. Part I, No. 2B, pp. 941-945 (1996)
31. A. Iwata and M. Nagata,
    A Concept of Analog-Digital merged Circuit Architecture for Future VLSI's,
    Analog Integrated Circuits and Signal Processing, Vol.11, No.2, pp.83-96, (1996).
32. T. Doi, A. Iwata and M. Hirose,
    Analysis and Design of Low Loss and Low Mode-Shift Integrated Optical Waveguides
    Using Finite-Difference Time-Domain Method,
    IEICE Trans. Electronics, Vol. E80-C, No.5, pp.625-631, (1997).
33. T. Morie, S. Sakabayashi, M. Nagata and A. Iwata,
    Nonlinear function generators and Chaotic sugnal generators using a pulse-width modulation method��
    Electronics letters, Vol.33, No. 16, pp.1351-1352, 31, July, 1997.
34. M. Saen, T. Morie, M. Nagata and A. Iwata,
    A Stochastic Associative Memory using Single-Electron Tunneling Devices,
    IEICE Trans. Electronics, Vol. E81-C, No.1, pp.30-35, 1998. [pdf]
35. M. Nagata, J. Funakoshi and A. Iwata,
    A PWM Signal Processing Core Circuit Based on a Switched Current Integration Technique,
    IEEE Journal of Solid-State Circuits, Vol.33, No.1, pp.53-59, 1998. [pdf]
36. T. Doi, A. Uehara, Y. Takahashi, S. Yokoyama, A. Iwata and M. Hirose,
    An Experimental Pattern Recognition System Using Bidirectional Optical Bus Lines,
    Jap. J. Appl. Phys., Vol. 37, Part I, No. 3B, pp.1116-1121, (1998).
37. M. Nagata and A. Iwata,
    PWM Signal Processing Architecture for Intelligent Systems,
    Computers & Electrical Engineering, Vol. 23, No. 6, pp.393-405, 1997
38. 岩田��永田��森��,
    アナログ・����タル融合回路による知能処��LSI,
    電子情報通信学会誌，Vol. 81, No. 9, pp.893-897, 1998.
39. 雨宮��岩田������,
    単電子回路による知能����デバイスの可能性,
    電子情報通信学会誌，Vol. 81, No. 9, pp.898-902, 1998.
40. M. Nagata and A. Iwata,
    Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design (Invited)
    IEICE Trans. Fundamentals, Vol. E82-A, No.2, pp.271-278, 1999. [pdf]
41. T. Morie, J. Funakoshi, M. Nagata and A. Iwata,
    An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique,
    IEICE Trans. Fundamentals, Vol. E82-A, No.2, pp.356-363, 1999.
42. A. Iwata, N. Sakimura, M. Nagata and T. Morie,
    The Architecture of Delta Sigma, Analog-to-Digital Converter using Voltage-Controlled Oscillator
    as a Multibit Quantizer,
    IEEE Trans. Circuits and Systems-II, Vol. 46, No.7, pp.941-945, 1999. [pdf]
43. S. Kinoshita, T. Morie, M. Nagata and A. Iwata,
    New Non-Volatile Analog Memory Circuits Using PWM Methods,
    IEICE Trans. Electron., Vol. E82-C, No. 9, pp. 1655-1661, 1999. [pdf]
44. T. Morie, K. Uchimura, Y. Amemiya,
    Analog LSI Implementation of Self-Learning Neural Networks,
    Computers and Electrical Engineering, Vol. 25, No. 5, pp. 339-355, 1999.
45. H. Ando, T. Morie, M. Nagata and A. Iwata,
    A Nonlinear Oscillator Network for Gray-level Image Segmentation and PWM/PPM Circuits
    for its VLSI Implementation,
    IEICE Trans. Fundamentals, Vol. E83-A, No. 2, pp. 329-336, 2000.
46. T. Morie, T. Matsuura, S. Miyata, T. Yamanaka, M. Nagata and A. Iwata,
    Quantum Dot Structures Measuring Hamming Distance for Associative Memories,
    Superlattices and Microstructures, Vol. 27, No. 5/6, pp. 613-616, 2000.
47. T. Yamanaka, T. Morie, M. Nagata and A. Iwata,
    A single-electron stochastic associative processing circuit robust to random background-charge effects
    and its structure using, nanocrystal floating-gate transistors,
    Nanotechnology, Vol. 11, No. 3, pp. 154-160, 2000.
48. M. Nagata, J. Nagai, T. Morie, and A. Iwata,
    Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC Environment,
    IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 6, pp. 671-678, 2000.
49. T. Morie, S. Sakabayashi, M. Nagata and A. Iwata,
    CMOS Circuits Generating Arbitrary Chaos by Using Pulse Width Modulation Techniques,
    IEEE Trans. Circuits and Systems-I, Vol. 47, No. 11, pp. 1652-1657, 2000.[pdf]
50. A. Iwata, T. Morie, and M. Nagata,
    Merged Analog-Digital Circuits Using Pulse Modulation for Intelligent SoC Applications (Invited),
    IEICE Trans. Fundamentals, Vol. E84-A, No. 2, pp. 486-496, 2001. [pdf]
51. M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata,
    Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits,
    IEEE J. Solid-State Circuits, Vol. 36, No. 3, pp. 539-549, 2001. [pdf]
52. S. Kinoshita, T. Morie, M. Nagata and A. Iwata��
    A PWM Analog Memory Programming Circuit for Floating-Gate MOSFETs with 75us Programming Time
    and 11b Updating Resolution��
    IEEE J. Solid-State Circuits, Vol. 36, No. 8, pp. 1286-1290, 2001.
53. T. Yamanaka, T. Morie, M. Nagata, and A. Iwata��
    A CMOS Stochastic Associative Processor Using PWM Chaotic Signals��
    IEICE Trans. Electronics, Vol. E84-C, No. 12, pp. 1723-1729, 2001. [pdf]
54. H. Ando, T. Morie, M. Miyake, M. Nagata and A. Iwata,
    Image Segmentation/Extraction Using Nonlinear Cellular Networks and their VLSI Implementation
    Using Pulse-Modulation Techniques,
    IEICE Trans. Fundamentals, Vol. E85-A, No. 2, pp. 381-388, 2002.
55. T. Morie and T. Matsuura and M. Nagata and A. Iwata,
    A Multi-Nano-Dot Circuit and Structure Using Thermal-Noise Assisted Tunneling
    for Stochastic Associative Processing,
    J. Nanosci. Nanotech., Vol. 2, No. 3, pp. 343-349, June, 2002.
56. K. Katayama, M. Nagata, T. Morie and A. Iwata,
    An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing,
    IEICE Trans. Electron., Vol. E85-C, NO.8, pp. 1596-1603, Aug. 2002. [pdf]
57. 岩田　��,
    高機��アナログ・����ジタル混載シス����LSI技��,
    電子情報通信学会論文��, VOL.J85-C NO.9, 9��, 2002年 [pdf]
58. T. Morie, T. Matsuura, M. Nagata, and A. Iwata
    A Multi-Nanodot Floating-Gate MOSFET Circuit for Spiking Neuron Models
    IEEE Trans. Nanotechnology, Vol. 2, No. 3, pp. 158-164, Sept. 2003.
59. T. Yoshida, T. Mashimo, M. Akagi, A. Iwata, M. Yoshida and K. Uematsu,
    A Design of Neural Signal Sensing LSI with Multi-Input Channels,
    IEICE Trans. Fundamentals, Vol. E87-A, No. 2, pp. 376-383, Feb. 2004. [pdf]
60. T. Morie, K. Murakoshi, M. Nagata and A. Iwata,
    Pulse Modulation Techniques for Nonlinear Dynamical Systems and a CMOS Chaos Circuit with Arbitrary 1-D Maps,
    IEICE Trans. Electron., Vol. E87-C, No. 11, pp. 1856-1862. November, 2004.
61. T. Yoshida, M. Akagi, T. Mashimo, A. Iwata, M. Yoshida and K. Uematsu,
    A Design of Wireless Neural-Sensing LSI,
    IEICE Trans. Electronics, Vol. E87-C, No. 6, pp. 996-1002. June 2004. [pdf]
62. T. Yoshimura and A. Iwata,
    An analysis of interference in synchronous systems,
    IEICE Electronics,Express, Vol. 1, No. 15, pp. 465-471, 2004.
63. M. Shiozaki, T. Mukai, M. Ono, M. Sasaki, A. Iwata,
    A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique,
    IEICE Trans. Electron., Vol. E88-C, No. 6, pp.1233-1240, June 2005. [pdf]
64. M. Shiozaki, T. Mukai, M. Ono, M. Sasaki, A. Iwata,
    A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors,
    Journal of Robotics and Mechatronics, Vol. 17, No. 4, pp. 463-468, August 2005.
65. M. Shiozaki, M. Sasaki, A. Mori, A. Iwata, and H. Ikeda,
    20GHz Uniform-Phase Uniform-Amplitude Standing-Wave Clock Distribution,
    IEICE Electronics Express (FLEX), Vol. 3, No. 2, pp. 11-16, 2006.
66. T. Yoshimura, A. Iwata,　　　　IEEE Darlington Award 受賞論文
    A Study of Interference in Synchronous Systems,
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, Vol. 53,　No. 8, pp. 1726-1740, Aug, 2006.[pdf]
67. K. Sasaki, T. Morie, and A. Iwata,
    A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory,
    IEICE Trans. Electron., Vol. E89-C, No. 11, pp. 1637-1644, November 2006. [pdf]
68. M. Hori, M, Ueda and A. Iwata,
    Stochastic Computing Chip for Measurement of Manhattan Distance,
    Japanese Journal of Applied Physics, Vol. 45, No. 4B, pp. 3301-3306, 2006.
69. T. Yoshida, Y. Masui, T. Mashimo, M. Sasaki and A. Iwata,
    A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique,
    IEICE Trans. Electrons., Vol. E89-C, No.6, pp. 769-774, Jun. 2006. [pdf]
70. D. Kosaka, M. Nagata, Y. Murasaka, A. Iwata
    Evaluation of Isolation Structures against High-Frequency Substrate Coupling
    in Analog/Mixed-Signal Integrated Circuits,
    IEICE Trans. Electron., Vol. E90-A, No. 2, pp. 380-387, February 2007.
71. Y. Masui, T. Yoshida, M. Sasaki and A. Iwata
    A 0.6V Supply Complementary Metal Oxide Semiconductor Amplifier
    Using Noise Reduction Technique of Autozeroing and Chopper Stabilization,
    Japanese Journal of Applied Physics, Vol. 46, No. 4B, pp. 2252-2256, 2007
72. T. Yoshida, N. Ishida, M. Sasaki and A. Iwata
    Low-Voltage, Low-Phase-Noise Ring Voltage-Controlled Oscillator Using 1/f-Noise Reduction Techniques
    Japanese Journal of Applied Physics, Vol. 46, No.4B, pp. 2257-2260, 2007.
73. A. Iwata, T. Yoshida, M. Sasaki
    Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices
    IEICE Trans. Electron., Vol. E90-C, No. 6, pp. 1149-1155, June 2007. [pdf]
74. D. Kosaka, M. Nagata Y. Murasaka and A. Iwata,
    Chip-Level Substrate Coupling Analysis with Reference Structures for Verification,
    IEICE Trans. Fundamentals, Vol.E90-A, No.12, pp. 2651-2660, Dec.1, 2007.
    
75. H. Ando, S. Kameda, D. Arizono, N. Fuchigami, K. Kaya, M. Sasaki, and A. Iwata
    Principal Component Analysis-Based Object Detection/Recognition Chip
    for Wireless Interconnected Three-Dimensional Integration,
    Japanese Journal of Applied physics, Vol. 47, No. 4, pp. 2746-2748, April 25, 2008.
76. A. Toya, Y. Murasaka, T. Ohmoto, and A. Iwata
    Evaluation of Digital Crosstalk Noise on Differential Input Voltage Controlled Oscillator,
    Japanese Journal of Applied physics, Vol. 47, No. 4, pp. 2742-2745, April 25, 2008.
77. Y. Masui, T. Yoshida and A. Iwata,
    Low power and low voltage chopper amplifier without LPF,
    IEICE Electronics Express, vol.5, No.22, pp.967-972, 2008
78. Y. Masui, T. Yoshida and A. Iwata,
    A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion,
    IEICE Trans. on Electronics, Vol.E92-C, No.6 pp.828-834, June 1, 2009. [pdf]
    
79. K. Gotoh, H. Ando, and A. Iwata,
    A 1.0-V 10-b 30-MS/s 3.4-mW rail-to-rail pipelined ADC using a new front-end MDAC,
    IEICE Electronics Express, vol.6, No.4, pp.198-204, 2009.
80. T. Yoshida, Y. Masui, R. Eki, A. Iwata, M. Yoshida and K. Uematsu,
    A Neural Recording Amplifier with Low-Frequency Noise Suppression,
    IEICE Trans. on Electronics, Vol.E93-C, No.6 pp.849-854, June, 2010.[pdf]
    
81. 亀田成司, 森山祐��, 野田健一, 岩田　����
    ルシフェラーゼによる生物発光を検��可能な高感度バイオフォトセンサの開発
    計測自動制御学会論文�� vol.47, No.25-30, 2011.
82. T. Yoshida, K. Sueishi, A. Iwata, K. Matsushita, M. Hirata, and T. Suzuki��
    A High-Linearity Low-Noise Amplifier with Variable Bandwidth for Neural Recoding Systems,
    Jpn. J. Appl. Phys., vol.50, 04DE07, 2011.
83. A. Iwata, Y. Murasaka, T. Maeda, and T. Ohmoto,
    Background Calibration Techniques for Low-power and High-speed Data Conversion,
    IEICE Trans. Electron., Vol. E94-C, No. 6, pp. 923-929, June 2011.[pdf]
84. S. G. Ryu, T. G. Tsuru, S. Nakajima, A. Takeda, Y. Arai, T. Miyoshi, R. Ichimiya,
    Y. Ikemoto, H. Matsumoto, T. Imamura, T. Ohmoto, A. Iwata,
    First Performance Evaluation of an X-Ray SOI Pixel Sensor for maging Spectroscpy and Intra-Pixel Trigger,
    IEEE Trans. Nuclear Sci., Vol. 58, No. 5, pp. 2528-2536, Oct. 2011.
85. K. Shimonomura, S. Kameda A. Iwata, and T. Yagi,
    Wide-Dynamioc-Range APS-Based Silicon Retina with Brightness Constancy,
    IEEE Trans. Meural Networks., Vol. 22, No. 9, pp. 1482-1493, Sept. 2011.
86. S. G. Ryu, T. G. Tsuru, G. Prigoxhin, S. Kissel, M. Bautz, B. LaMarr, S. Nakajima,
    R. F. Foster, A. Takeda, Y. Arai, T. Imamura, T. Ohmoto, A. Iwata,
    Tests with Soft X-Rays of an Improved Monolithic SOI Active Sensor ,
    IEEE Trans. Nuclear Sci., Vol. 60, No. 1, pp. 465-469, Jan. 2013.
87. A. Takeda, Y. Arai, S. G. Ryu, S. Nakajima, T. G. Tsuru, T. Imamura, T. Ohmoto, A. Iwata
    Design and Evaluation of an SOI Pixel Sensor for Trigger-Driven X-Ray Readout,
    IEEE Trans. Nuclear Sci., Vol. 60, No. 2, pp. 586-591, April 2013.
88. T. Kikkawa, Y. Masui, A. Toya, H. Ito, T. Hirano, T. Maeda, M. Ono, Y. Murasaka, T. Imamura,
    T. Matsumaru, M.Yamaguchi, Sunagawa, A. Azhari, H. Song, S. Sasada, A. Iwata,
    CMOS Gaussian Monocycle Pulse Tranceiver for Rader-Based Microwave Imaging,
    IEEE Trans. Biomedical Circuits and Systems, Vol. 14, No. 6, pp. 1333-1345, Dec. 2020.